The present invention relates to a wiring structure in a multilayer printed wiring board or component-embedded printed wiring board.
Multilayer printed wiring boards obtained by alternately stacking an insulating layer and a wiring layer and component-embedded printed wiring boards having an insulating layer with electronic component-embedded therein are known as a high density packaging structure of electronic components such as semiconductor IC chips. In printed wiring boards having such a structure, as a method for connecting a wiring layer to a body to be wired thereto such as an underlying wiring layer or an electrode of an embedded electronic component arranged below or inside the insulating layer, a method for forming, in the insulating layer, a connection hole which is called “via-hole” to expose therefrom the body to be wired and connecting the body to be wired and the wiring layer inside the via-hole (refer to Japanese Patent Laid-Open Nos. 2006-100773 and 2005-64470) is known.
For the manufacture of wiring structure, three processes are generally known. They are an additive process of selectively forming a wiring layer at a wiring pattern portion; a semi-additive process of forming a background layer over the entire surface of a substrate, selectively removing or masking a portion of the background layer other than the wiring pattern portion, and forming a wiring layer on the background layer which has remained or is exposed in the pattern form; and a subtractive process of forming a conductor layer over the entire surface of a substrate and then selectively removing a portion of the conductor layer other than a wiring pattern portion to form a wiring layer. These manufacturing processes of wiring structure are also employed commonly for the via-hole connection, that is, connection of a wiring layer and a body to be wired in a via-hole.
For example, there is disclosed in Japanese Patent Laid-Open No. 2006-100773 a process (subtractive process) of forming, in a multilayer printed wiring board, a conductor layer over the entire surface of a substrate including the inner wall of a via-hole, and selectively removing a portion of the conductor layer other than a wiring pattern portion by photolithography and etching to form the wiring pattern.
In Japanese Patent Laid-Open No. 2005-64470, there is disclosed a process (semi-additive process) of forming, in a component-embedded printed wiring board, an underlying conductive layer over the entire surface of a substrate including the inner wall of a via-hole, masking a portion of the underlying conductive layer other than a wiring pattern portion and carrying out electroplating with the exposed underlying conductive layer as a base to form the wiring pattern.